nagra 0501: fix map04 timing

diff --git a/systems/nagra/nagra2-0501.c b/systems/nagra/nagra2-0501.c
index ae6e8a7b7473437dff48584b4f4432b3dac73227..04a0d78aca211db3d0a841417b906dddaed57351 100644 (file)
--- a/systems/nagra/nagra2-0501.c
+++ b/systems/nagra/nagra2-0501.c
@@ -127,7 +127,7 @@ bool cN2Prov0501::RomInit(void)
 bool cN2Prov0501::ProcessMap(int f)
 {
   unsigned short addr;
-  int size=wordsize<<3;
+  int size;
   unsigned char tmp[256];
 
   switch(f) {
@@ -144,8 +144,8 @@ bool cN2Prov0501::ProcessMap(int f)
     case IMPORT_C:
     case IMPORT_D:
     case IMPORT_LAST:
-      addr=HILO(0x44);
-      GetMem(addr,tmp,size,0); DoMap(f,tmp);
+      addr=HILO(0x44); size=Get(0x48);
+      GetMem(addr,tmp,size<<3,0); DoMap(f,tmp,size);
       AddCycles(MapCycles());
       break;
     case EXPORT_J: //Export Registers A-E with 44:45: 0x09 is E
@@ -154,15 +154,15 @@ bool cN2Prov0501::ProcessMap(int f)
     case EXPORT_C:
     case EXPORT_D:
     case EXPORT_LAST:
-      addr=HILO(0x44);
-      DoMap(f,tmp); SetMem(addr,tmp,size,0);
+      addr=HILO(0x44); size=Get(0x48);
+      DoMap(f,tmp,size); SetMem(addr,tmp,size<<3,0);
       break;
     case SWAP_A: //Swap Registers A-D with 44:45
     case SWAP_B:
     case SWAP_C:
     case SWAP_D:
-      addr=HILO(0x44);
-      GetMem(addr,tmp,size,0); DoMap(f,tmp); SetMem(addr,tmp,size,0);
+      addr=HILO(0x44); size=Get(0x48);
+      GetMem(addr,tmp,size<<3,0); DoMap(f,tmp,size); SetMem(addr,tmp,size<<3,0);
       break;
     case CLEAR_A:
     case CLEAR_B:

diff --git a/systems/nagra/nagra2.c b/systems/nagra/nagra2.c
index 746b966869c9fc093cea0317ae4ea3ef1bd685cb..671b4a2ed7c2db5bc980fe1e6486a6f98ce52a8d 100644 (file)
--- a/systems/nagra/nagra2.c
+++ b/systems/nagra/nagra2.c
@@ -460,9 +460,12 @@ bool cMapCore::DoMap(int f, unsigned char *data, int l)
       last=f-IMPORT_J;
       // fall through
     case IMPORT_LAST:
-      regs[last]->GetLE(data,last>0?dl:8);
-      cycles=944; // certainly dependant on the wordsize, but for now enough for PW
+      {
+      int s=last>0?dl:8;
+      regs[last]->GetLE(data,s);
+      cycles=772+160*(s>>3); // stil not sure if correct
       break;
+      }
 
     case EXPORT_J:
     case EXPORT_A: